Fabrication of lateral superjunction devices using selective epitaxy

ABSTRACT

A lateral superjunction includes a substrate layer, a selective epitaxy layer deposited on the substrate layer, a trench formed into the selective epitaxy layer to expose a portion of the substrate layer, a first layer of semiconductor deposited in the trench, a second layer of semiconductor deposited adjacent to the first layer, and a first end layer of semiconductor deposited adjacent to the first layer of semiconductor and a second end layer of semiconductor deposited adjacent to the second layer of semiconductor.

CROSS-REFERENCES TO RELATED APPLICATIONS

This application is a continuation of U.S. patent application Ser. No.16/642,283, filed on Feb. 26, 2020. U.S. patent application Ser. No.16/642,283 is a national stage entry of PCT/US2018/053572, filed on Sep.28, 2018, which claims priority to U.S. Provisional Patent ApplicationNo. 62/566,290, filed on Sep. 29, 2017. All of the aforementionedapplications are hereby incorporated by reference in their entirety.

BACKGROUND Technical Field

The present disclosure relates generally to the manufacture of improved(i.e., increased reliability and decreased cost) power electronicsdevices capable of handling high voltage with low on resistances. Forexample, and not by way of limitation, the present disclosure relates tofabrication of lateral superjunctions using selective epitaxy.

HISTORY OF RELATED ART

Work has been done on superjunctions but, to date, no one has providedlow-defect (e.g., below 10⁶ cm⁻²) lateral superjunction GaN devicesgrown on a relatively inexpensive (silicon or sapphire) substrate.Current devices are unable to achieve high breakdown voltages at lowon-resistances.

BRIEF SUMMARY

In an exemplary aspect, a lateral superjunction includes a substratehaving a trench; a first doped GaN layer deposited within the trench anddisposed on a surface of the substrate; a plurality of doped GaN layersdisposed on the first GaN layer and disposed on each of the plurality ofdoped GaN layers; a first doped GaN sidewall structure disposed on thesurface of the substrate and adjacent to the plurality of doped GaNlayers; and a second doped GaN sidewall structure disposed on thesurface of the substrate.

In another exemplary aspect, a method of preparing a lateralsuperjunction includes: 1) selecting a substrate and nucleation layersthat favor GaN growth; 2) performing selective epitaxy to formalternating p/n layers in-situ; 3) etching GaN film to definesuperjunction device dimensions; 4) Regrow p+ and n+ ohmic contactregions; and 5) depositing ohmic contacts (metals) to p+ and n+ regrownregions.

Aspects of the disclosure can be implemented using standardsemiconductor process equipment. By way of example, an illustrativemethod of forming a superjunction includes the following steps:

1) selecting a substrate (e.g., silicon or sapphire) on which to deposita layer of GaN;

2) depositing (grow epitaxially) a high quality GaN buffer layer;

3) depositing a selective epitaxy mask;

4) patterning a selective epitaxy mask to achieve an aspect ratio of atleast one to trap defects that occur during growth in the opening;

5) growing alternating layers of p-type and n-type semiconductor;

6) depositing a masking layer to act as a hard mask during a subsequentetching process;

7) etching areas of GaN using a wet or dry etch to achieve a desiredsuperjunction device structure;

8) removing the hard mask and/or depositing a new mask layer to allowfor the p+ or n+ growth to happen from a sidewall of the superjunctionstructure;

9) repeating the previous step for either the p+ or n+ layer; and

10) performing ohmic contact metallization to the p+ and n+ layer tocomplete device fabrication.

In some aspects, a method of producing a lateral superjunction includesthe steps below:

1) Selecting a wafer substrate (e.g., silicon, sapphire, siliconcarbide, GaN, Ga₂O₃, GaAs, SiO₂, etc.).

2) Depositing layer(s) material to act as a nucleation site forsubsequent selective epitaxy (e.g., deposit AlN, GaN, InN or any ofcombination of the three). Thickness and composition are highlydependent on diameter of substrate. In some aspects, this step may beomitted if the substrate obtained in step one works as a good nucleationsite for the selective epitaxy in the following steps (e.g., bulk GaNsubstrates). For example, typically on silicon substrates, AlN isdeposited directly on the silicon, then graded AlxGa1-xN buffer layersare deposited on top of the AlN, and finally a GaN layer is deposited ontop of the graded AlxGa1-xN. This is done to manage thermal and latticemismatch between the substrate and the GaN layer. In some aspects, thefinal “starting material” before selective epitaxy is comprised of thefollowing layers: bulk silicon substrate/AlN/AlxGa1-xN/GaN.

3) Depositing, on the starting material, an amorphous layer usingphysical vapor deposition (PVD) or chemical vapor deposition (CVD) thatwill act as a mask during the selective epitaxy step. Thickness of thislayer can vary. In some aspects, the thickness can be between 10nanometers to 10 microns. In some aspects, metals can be used as aselective epitaxy mask. While metals are more polycrystalline thanamorphous, metals can provide the selective nature of deposition insubsequent epitaxy steps.

4) Forming, using patterning techniques (e.g., optical lithography,nano-imprint lithography, electron beam lithography, etc.), an openingin the amorphous layer described in the previous step.

5) Inserting the wafer substrate into deposition tool to formsuperjunction layers. Though GaN-based superjunctions are discussed inthis illustrative example, materials other than GaN can be used. Forexample, other acceptable materials include GaAs, SiC, InN, AlN, Ga₂O₃and any other semiconductor that can be doped n-type and p-type.Suitable deposition tools include MOCVD, MBE, HVPE, Evaporation,Sputter, LPE, and various other PVD or CVD techniques.

6) Depositing, in-situ, alternating layers of p-type and n-typesemiconductors. Layering can begin with either p-type or n-typematerial, but we should not restrict ourselves to this example. Thenumber of layers, thickness and doping density of each layer depends onthe application.

7) Depositing a mask that will allow for etching of the alternatingsuperjunctions layers. This mask can be photoresist, dielectric, metalor another semiconductor.

8) Etching the superjunction layers. Etching can be performed using dryetching (e.g., plasma based etching) or wet etching (e.g., liquids,specifically acids).

9) Depositing another mask for subsequent regrowth of p+ and n+ contactregions. In some aspects, removal of the mask of step 7 is notnecessary.

10) Regrowing p+ or n+ contact regions at exposed ends of the p-type andn-type layers using any deposition technique highlighted in step 5.

11) Depositing n-type or p-type ohmic contacts. Many different kinds ofsurface treatments can be applied to the semiconductor surface beforethe metal is deposited. For example, surface treatments using acids(e.g., HCl, HF, HNO₃), bases (e.g., NaOH, KOH), or plasmas (fluorine,chlorine, oxygen based) may be utilized. Furthermore, the metal(s)deposited may be exposed to thermal anneal after deposition.

BRIEF DESCRIPTION OF THE DRAWINGS

The disclosure is best understood from the following detaileddescription when read with the accompanying figures. It is emphasizedthat, in accordance with standard practice in the industry, variousfeatures are not drawn to scale. In fact, the dimensions of variousfeatures may be arbitrarily increased or reduced for clarity ofdiscussion.

FIGS. 1-3 illustrate methods of making a superjunction according tovarious aspects of the disclosure;

FIGS. 4 and 5 illustrate superjunction mask designs according variousaspects of the disclosure;

FIG. 6 is a graph of column width versus column doping density;

FIG. 7 is a schematic view of an illustrative superjunction;

FIG. 8 is a graph of specific on-resistance versus breakdown voltage forthe illustrative superjunction of FIG. 7;

FIG. 9 is a graph of figure of merit versus column doping density forthe illustrative super junction of FIG. 7;

FIGS. 10A and 10B are graphs of electric field versus transverse andperpendicular distances for the illustrative super junction of FIG. 7;

FIG. 11 is a graph of current versus voltage for the illustrative superjunction of FIG. 7;

FIG. 12 is a graph of the log of the current of FIG. 11 versus voltagefor the illustrative super junction of FIG. 7;

FIG. 13 is a graph of simulated breakdown voltage versus chargeimbalance;

FIG. 14 is a graph comparing electric field versus distance forsuperjunction devices with different charge imbalances;

FIG. 15 is a graph of doping density versus distance for differentgraded profile values;

FIG. 16 is a graph of relative charge versus graded profile value fordifferent on-resistances, breakdown voltages, and figures of merit; and

FIG. 17 is a graph of specific on-resistance versus breakdown voltage.

DETAILED DESCRIPTION

Embodiment(s) of the disclosure will now be described more fully withreference to the accompanying Drawings. The disclosure may, however, beembodied in many different forms and should not be construed as limitedto the embodiment(s) set forth herein. The disclosure should only beconsidered limited by the claims as they now exist and the equivalentsthereof.

Disclosed is a process for forming a lateral superjunction device on asilicon or sapphire substrate having doped GaN layers with favorabledefect density (i.e., close to zero) due to use of a selective epitaxytechnique. The lateral superjunction of the present disclosure isdirected to the problem of manufacturing low-defect power electronicswith high breakdown voltages and low on-resistance from GaN deposited oninexpensive (silicon or sapphire) substrates. Use of the describedprocess decreases defects with a concomitant enhancement of deviceperformance. In particular, devices manufactured with the disclosedprocess exhibit higher break-down voltages and lower on-resistances.

The lateral superjunction disclosed herein can be used to manufacturesuperior electronic devices that can be combined in an electroniccircuit to improve efficiency in low and high power applications.Furthermore, the procedure described herein can reduce manufacturingcosts and increase yields of current technologies. Power electronicapplications require a lateral or vertical electronic device to be ableto conduct electricity with minimal resistance during the on-state andbe able to block high voltages during the off-state. However, materialand device trade-offs exist such that it is difficult to achieve both ofthese attributes in a power electronic device. Material defects haveproven to be detrimental to device operation and yield. The disclosureimproves material quality by reducing defects through trapping in asmall opening during the growth. This technique is known as selectivearea epitaxy (also sometimes referred to as nano-heteroepitaxy or aspectratio trapping) in the semiconductor industry. Device design is improvedby adopting standard silicon technology known as a superjunction.Alternating layers of n-type and p-type semiconductor material is acharacteristic of the superjunction and produces an electronic devicethat is able to conduct electricity well in the on-state and block highvoltages in the off-state. The utilization of selective epitaxy and alateral superjunction produce a device with superior electricalperformance, while also increasing yield and reliability in themanufacturing process.

The disclosure allows for current device performance to be greatlyexceeded. The semiconductor industry continues to strive for integrationand miniaturization. This disclosure allows for both integration andminiaturization of power electronics by describing a process that istransferable to any substrate and can be integrated on chip with siliconcontrol electronics, significantly reducing the footprint and parasiticsof an electronics circuit board has in a given product.

Synthesis of separate semiconductor processing techniques and devicedesign take advantage of breakthroughs in semiconductor fabrication.Gallium-nitride (GaN) based electronics have struggled to perform aswell as theoretically predicted. GaN-based electronics that performclose to theoretical limits have recently been manufactured. It wasfound that a reduction in defect density and the utilization of dopedGaN lead to improved device operation. However, the fabrication processused is vertical in nature and requires expensive substrates that aredifficult to manufacture and scale to larger diameters for costreduction. In contrast, the disclosure described herein uses lateraldevices that exhibit similar defect densities and alternating layers ofdoped GaN to produce devices termed superjunctions.

Superjunctions are a well-developed technology for silicon-basedelectronics, but are not manufactured using GaN due to difficultiesrelated to manufacturing p-type GaN and making proper electronic contactto the material. These difficulties are overcome with the lateral natureof the fabrication process disclosed herein that allows for trivialscaling procedures and for inexpensive substrates to be used (i.e.,silicon and sapphire). Other substrates, such as silicon carbide andbulk GaN substrates cost 5× to 50× more than the silicon and sapphiresubstrates. While vertical superjunction device technology based onsilicon has been in the industry for decades and has proven to beextremely successful, lateral superjunctions made from silicon have notperformed as well as the vertical devices due to substrate depletioneffects and poor dopant distribution control from ion implantation. Thenovel process outlined herein does not suffer from substrate depletionbecause of the selective epitaxy technique. The novel process outlinedherein reduces substrate depletion effects while eliminating damage anddopant distribution issues associated with ion implantation.

In some aspects, magnesium is used as a dopant for the GaN. Magnesiumdiffuses significantly at temperatures used for growth. Techniques tominimize the diffusion are crucial to ensure proper device operation.For example, films with high defect densities will have strong dopantdiffusion. However, if defects are properly reduced then dopantdiffusion is also significantly reduced. Furthermore, highly doped GaNmust be regrown or created by ion implantation to allow for a propermetal/semiconductor contact to be formed. Development of the regrown GaNand its impact on Mg diffusion is another critical piece of knowledge tobe obtained. Bulk GaN substrates have low defect densities (<10⁵ cm⁻²),which is desirable. However, bulk GaN has a slow growth rate forsubstrate formation, is expensive (e.g., two inch wafers are extremelyexpensive), and scaling of bulk GaN substrates to reduce cost has provendifficult. In contrast, forming selective GaN on silicon substrates isrelatively inexpensive and scales well, while at the same time providessimilarly low defect densities (<10⁶ cm⁻²).

TABLE 1 GaN Superjunction compared to other configurations TechnologyComparison Silicon GaN/Si 4H-SiC GaN/GaN GaN SJ Normalized Wafer +  1 1.7  6 60  2.1 epi cost ($-mm⁻²) Defects (cm⁻²)  <1  10⁹  10³->10⁴10⁴->10⁶ <10⁶ Wafer diameter 300 150 150 50 200 (mm) Avalanche Yes NoYes Yes Yes Breakdown Current No Yes No No No Collapse/Dynamic R_(ON)

Referring now to FIG. 1, a method 100 of making a superjunction 132 isillustrated according to various aspects of the disclosure. Forillustrative purposes, method 100 is shown in in five stages I-V. StageI includes steps (a)-(c), stage II includes steps (a)-(d), and so on.

In stage I, a substrate 102 is selected and prepared for deposition ofsuperjunction layers. In step I(a), a substrate 102 is selected. Varioussubstrates may be used including silicon and sapphire. In step I(b), alayer 104 is deposited on substrate 102. Layer 104 is a nucleation layerof amorphous or dielectric material and acts as a mask during selectiveepitaxy. Layer 104 is chosen to be a material that does not facilitategrowth of material for the superjunction. In some aspects, layer 104 isGaN. In other aspects, layer 104 could be one or more of AlN, InN, GaN,SiN, or SiO₂. Thickness and composition of layer 104 are highlydependent on the diameter of substrate 102. Layer 104 can be depositedon the substrate using various techniques. For example, layer 104 can bedeposited using PVD or CVD techniques. In some aspects, metals such astungsten can be used as a selective epitaxy mask. While these metals aremore poly crystalline than amorphous, the metals can still be effective.

In some aspects, step I(b) may be omitted if the substrate obtained instep I(a) works as a good nucleation site for the selective epitaxy inthe following steps (e.g. bulk GaN substrates). In some aspects, onsilicon substrates, AlN is deposited directly on the silicon, gradedAlxGa1-xN buffer layers are deposited on top of the AlN, and finally aGaN layer is deposited on top of the graded AlxGa1-xN. This is done tomanage thermal and lattice mismatch between the substrate and the GaNlayer. In some aspects, the final starting material before selectiveepitaxy is comprised of the following layers: bulk siliconsubstrate/AlN/AlxGa1-xN/GaN.

In step I(c), a patterning technique is used to form an opening 106 inlayer 104. Patterning techniques suitable for forming opening 106include optical lithography, nano-imprint lithography, electron beamlithography, etc. As illustrated in step I(c), opening 106 is in theform of a trench or groove that exposes a portion of substrate 102.

In stage II, layers of n-type and p-type semiconductors are depositedonto the product of stage I. In step II(a), a layer 108 is deposited inopening 106. Layer 108 may be an n-type or a p-type semiconductor. Forthe purposes of illustration of method 100, layer 108 is chosen to be ap-type semiconductor. In step II(b), a layer 110 is deposited on top oflayer 108. Layer 110 is an n-type semiconductor. In step II(c), a layer112 is deposited on top of layer 110. Layer 112 is a p-typesemiconductor. In step II(d), a layer 114 is deposited on top of layer112. Layer 114 is an n-type semiconductor. In some aspects, layer 108 isan n-type semiconductor, and layers 110, 112, and 114 are chosen so thatlayers of p-type and n-type semiconductor alternate. The number oflayers, thickness of each layer, and doping density of each layerdepends on the application. In some aspects, layer thickness can bebetween 10 nanometers and 10 microns. In some aspects, doping densitycan be between 10¹⁵ cm⁻³ and 10²⁰ cm⁻³.

Layers 108-114 can be deposited using various deposition techniques,including metal-organic chemical vapor deposition (MOCVD), molecularbeam epitaxy (MBE), hydride vapor phase epitaxy (HVPE), evaporationdeposition, sputter deposition, liquid-phase epitaxy (LPE), and variousother PVD or CVD techniques. Though GaN-based superjunctions arediscussed in this illustrative example, materials other than GaN can beused. For example, other acceptable materials include GaAs, SiC, InN,AlN, Ga₂O₃ and any other semiconductor that can be doped n-type andp-type.

In stage III, etching of the layers 108-114 is performed. In stepIII(a), a mask 116 is deposited on top of layer 114. In some aspects,mask 116 can be a layer of photoresist. In other aspects, other types ofmasks can be used including dielectrics, metals, or anothersemiconductor. In step III(b), an etching process is used to removeportions of layers 108-114 that are not beneath mask 116. Etching can beaccomplished using various techniques, including dry etching (e.g.,plasma based etching) or wet etching (e.g., using liquids such as acidsor bases). The etching of step III(b) leaves a stack of alternatinglayers of n-type and p-type semiconductors. In step III(c), mask 116 isremoved. In some aspects, mask 116 is not removed and is used in stageIV.

In stage IV, n-type and p-type contact regions are formed at endportions of layers 108-114. In step IV(a), a mask 118 is deposited tocover layers 108-114, but end portions 122 and 126 are left exposed. Insome aspects, mask 116 is left in place and mask 118 is deposited overmask 116. In some aspects, mask 118 can be a layer of photoresist. Inother aspects, other types of masks can be used including dielectrics,metals, or another semiconductor. In step IV(b), a first end layer 120is added to end portion 122 of superjunction 132 and an second end layer124 is added to end portion 126 of superjunction 132. First and secondend layers 120 and 124 are selected so that one of layers 120 and 124 isan n-type semiconductor and the other of layers 120 and 124 is a p-typesemiconductor. In some aspects, first end layer 120 is an n-typesemiconductor that couples to layers 110 and 114 and second end layer124 is a p-type semiconductor that couples to layers 108 and 112. Insome aspects, first end layer 120 is a p-type semiconductor that couplesto layers 108 and 112 and second end layer 124 is an n-typesemiconductor that couples to layers 110 and 114. First and second endlayers 120 and 124 can be deposited using various deposition techniques,including MOCVD, MBE, HVPE, evaporation deposition, sputter deposition,LPE, and various other PVD or CVD techniques. In step IV(c), mask 118(and mask 116 if mask 116 was not previously removed) is removed.

In stage V, ohmic contacts 128 and 130 are formed. In step V(a), ohmiccontacts 128 and 130 are deposited on layers 120 and 124. Ohmic contacts128 and 130 can be formed of various metals, including Al, Ti, Ni, Au,Ta and combinations thereof. In some aspects, various surface treatmentswith acids, bases, plasmas and combinations thereof can be applied to asurface of layers 120 and 124 before the metal for the ohmic contacts128 and 130 is deposited. In some aspects, the metal(s) deposited forthe ohmic contacts 128 and 130 may be exposed to thermal anneal afterdeposition.

Referring now to FIG. 2, a method 200 of making a superjunction 232 isillustrated according to various aspects of the disclosure. Forillustrative purposes, method 200 is shown in in five stages I-V. StageI includes steps (a)-(c), stage II includes steps (a)-(d), and so on.

In stage I, a substrate 202 is selected and prepared for deposition ofsuperjunction layers. In step I(a), a substrate 202 is selected. Varioussubstrates may be used including silicon and sapphire. In step I(b), alayer 204 is deposited on substrate 202. Layer 204 is a nucleation layerof amorphous or dielectric material and acts as a mask during selectiveepitaxy. In some aspects, layer 204 is GaN. In other aspects, layer 204could be one or more of AlN, InN, and GaN. Thickness and composition oflayer 204 are highly dependent on diameter of substrate. Layer 204 canbe deposited on the substrate using various techniques. For example,layer 204 can be deposited using PVD or CVD. In some aspects, metalssuch as tungsten can be used a selective epitaxy mask. While thesemetals are more poly crystalline than amorphous, the metals can still beeffective.

In some aspects, step I(b) may be omitted if the substrate obtained instep I(a) works as a good nucleation site for the selective epitaxy inthe following steps (e.g., bulk GaN substrates). For example, on siliconsubstrates, AlN is deposited directly on the silicon, graded AlxGa1-xNbuffer layers are deposited on top of the AlN, and finally a GaN layeris deposited on top of the graded AlxGa1-xN. This is done to managethermal and lattice mismatch between the substrate and the GaN layer. Insome aspects, the final starting material before selective epitaxy iscomprised of the following layers: bulk siliconsubstrate/AlN/AlxGa1-xN/GaN.

In step I(c), a patterning technique is used to form an opening 206 inlayer 204. Patterning techniques suitable for forming opening 206include optical lithography, nano-imprint lithography, electron beamlithography, etc. As illustrated in step I(c), opening 206 is in theform of a trench or groove that exposes a portion of substrate 202.

In stage II, layers of n-type and p-type semiconductors are depositedonto the product of stage I. In step II(a), a layer 208 is deposited inopening 206. Layer 208 may be an n-type or a p-type semiconductor. Forthe purposes of illustration of method 200, layer 208 is chosen to be ap-type semiconductor. In step II(b), a layer 210 is deposited on top oflayer 208. Layer 210 is an n-type semiconductor. In step II(c), a layer212 is deposited on top of layer 210. Layer 212 is a p-typesemiconductor. In step II(d), a layer 214 is deposited on top of layer212. Layer 214 is an n-type semiconductor. In some aspects, layer 208 isan n-type semiconductor, and layers 210, 212, and 214 are chosen so thatlayers of p-type and n-type semiconductor alternate. The number oflayers, thickness of each layer, and doping density of each layerdepends on the application. In some aspects, layer thickness can bebetween 10 nanometers and 10 microns. In some aspects, doping densitycan be between 10¹⁵ cm⁻³ and 10²⁰ cm⁻³.

Layers 208-214 can be deposited using various deposition techniques,including MOCVD, MBE, HVPE, evaporation deposition, sputter deposition,LPE, and various other PVD or CVD techniques. Though GaN-basedsuperjunctions are discussed in this illustrative example, materialsother than GaN can be used. For example, other acceptable materialsinclude GaAs, SiC, InN, AlN, Ga₂O₃ and any other semiconductor that canbe doped n-type and p-type.

In stage III, etching of the layers 208-214 is performed. In stepIII(a), an etching process is used to remove a upper portions of layers208-214. As illustrated in step III(a), a sufficient amount of materialis removed by the etching step so that an upper portion of each layer200-214 is exposed. The etching of step III(a) leaves alternating layersof n-type and p-type semiconductors arranged in a side by side position(e.g., conformal deposition). Etching can be accomplished using varioustechniques, including dry etching (e.g., plasma based etching) or wetetching (e.g., using liquids such as acids). In step III(b), a mask 216is deposited on top of layers 208-214. Mask 216 is positioned to leaveend portions 222 and 226 exposed.

In stage IV, n-type and p-type contact regions are formed at endportions of layers 208-214. In step IV(a), a first end layer 220 isadded to end portion 222 of superjunction 232 and a second end layer 224is added to end portion 226 of superjunction 232. First and second endlayers 220 and 224 are selected so that one of layers 220 and 224 is ann-type semiconductor and the other of layers 220 and 224 is a p-typesemiconductor. In some aspects, first end layer 220 is an n-typesemiconductor that couples to layers 210 and 214 and second end layer224 is a p-type semiconductor that couples to layers 208 and 212. Insome aspects, first end layer 220 is a p-type semiconductor that couplesto layers 208 and 212 and second end layer 224 is an n-typesemiconductor that couples to layers 210 and 214. First and second endlayers 220 and 224 can be deposited using various deposition techniques,including MOCVD, MBE, HVPE, evaporation deposition, sputter deposition,LPE, and various other PVD or CVD techniques. In step IV(b), mask 216 isremoved.

In stage V, ohmic contacts 228 and 230 are formed. In step V(a), ohmiccontacts 228 and 230 are deposited on layers 220 and 224. Ohmic contacts228 and 230 can be formed of various metals, including Al, Ti, Ni, Au,Ta and combinations thereof. In some aspects, various surface treatmentswith acids, bases, plasmas and combinations thereof can be applied to asurface of layers 220 and 224 before the metal for the ohmic contacts228 and 230 is deposited. In some aspects, the metal(s) deposited forthe ohmic contacts 228 and 230 may be exposed to thermal anneal afterdeposition.

Referring now to FIG. 3, a method 300 of making a superjunction 332 isillustrated according to various aspects of the disclosure. Forillustrative purposes, method 300 is shown in in five stages I-V. StageI includes steps (a)-(c), stage II includes steps (a)-(d), and so on.

In stage I, a substrate 302 is selected and prepared for deposition ofsuperjunction layers. In step I(a), a substrate 302 is selected. Varioussubstrates may be used including silicon and sapphire. In step I(b), alayer 304 is deposited on substrate 302. Layer 304 is a nucleation layerof amorphous or dielectric material and acts as a mask during selectiveepitaxy. In some aspects, layer 304 is GaN. In other aspects, layer 304could be one or more of AlN, InN, and GaN. Thickness and composition oflayer 304 are highly dependent on diameter of substrate. Layer 304 canbe deposited on the substrate using various techniques. For example,layer 304 can be deposited using PVD or CVD. In some aspects, metalssuch as tungsten can be used a selective epitaxy mask. While thesemetals are more poly crystalline than amorphous, the metals can still beeffective.

In some aspects, step I(b) may be omitted if the substrate obtained instep I(a) works as a good nucleation site for the selective epitaxy inthe following steps (e.g. bulk GaN substrates). For example, on siliconsubstrates, AlN is deposited directly on the silicon, graded AlxGa1-xNbuffer layers are deposited on top of the AlN, and finally a GaN layeris deposited on top of the graded AlxGa1-xN. This is done to managethermal and lattice mismatch between the substrate and the GaN layer. Insome aspects, the final starting material before selective epitaxy iscomprised of the following layers: bulk siliconsubstrate/AlN/AlxGa1-xN/GaN.

In step I(c), a patterning technique is used to form an opening 306 inlayer 304. Patterning techniques suitable for forming opening 306include optical lithography, nano-imprint lithography, electron beamlithography, etc. As illustrated in step I(c), opening 306 is in theform of a trench or groove that exposes a portion of substrate 302.

In stage II, layers of n-type and p-type semiconductors are depositedonto the product of stage I. In step II(a), a layer 308 is deposited inopening 306. Layer 308 may be an n-type or a p-type semiconductor. Forthe purposes of illustration of method 300, layer 308 is chosen to be ap-type semiconductor. In step II(b), a layer 310 is deposited on top oflayer 308. Layer 310 is an n-type semiconductor. In step II(c), a layer312 is deposited on top of layer 310. Layer 312 is a p-typesemiconductor. In step II(d), a layer 314 is deposited on top of layer312. Layer 314 is an n-type semiconductor. In step II(d), a layer 316 isdeposited on top of layer 314. Layer 316 is a p-type semiconductor. Insome aspects, layer 308 is an n-type semiconductor, and layers 310, 312,314, and 316 are chosen so that layers of p-type and n-typesemiconductor alternate. The number of layers, thickness of each layer,and doping density of each layer depends on the application. In someaspects, layer thickness can be between 10 nanometers and 10 microns. Insome aspects, doping density can be between 10¹⁵ cm⁻³ and 10²⁰ cm⁻³.

Layers 308-316 can be deposited using various deposition techniques,including MOCVD, MBE, HVPE, evaporation deposition, sputter deposition,LPE, and various other PVD or CVD techniques. Though GaN-basedsuperjunctions are discussed in this illustrative example, materialsother than GaN can be used. For example, other acceptable materialsinclude GaAs, SiC, InN, AlN, Ga₂O₃ and any other semiconductor that canbe doped n-type and p-type.

In stage III, etching of the layers 308-316 is performed. In stepIII(a), a mask 318 is deposited on top of layer 316. In some aspects,mask 318 can be a layer of photoresist. In other aspects, other types ofmasks can be used including dielectrics, metals, or anothersemiconductor. In step III(b), an etching process is used to removeportions of layers 308-316 that are not beneath mask 318. Etching can beaccomplished using various techniques, including dry etching (e.g.,plasma based etching) or wet etching (e.g., using liquids such asacids). The etching of step III(b) leaves a stack of alternating layersof n-type and p-type semiconductors. In step III(c), mask 318 isremoved. In some aspects, mask 318 is not removed and is used in stageIV.

In stage IV, n-type and p-type contact regions are formed at endportions of layers 308-316. In step IV(a), a mask 319 is deposited tocover layers 308-316 while leaving side portions 322 and 326 exposed. Insome aspects, mask 318 is left in place and mask 319 is deposited overmask 318. In some aspects, mask 319 can be a layer of photoresist. Inother aspects, other types of masks can be used including dielectrics,metals, or another semiconductor.

In step IV(b), a first end layer 320 is added to side portion 322 ofsuperjunction 332 and in step IV(c) a second end layer 324 is added toside portion 326 of superjunction 332. As illustrated in FIG. 3, firstand second end layers 320 and 324 are generally parallel to a length oftrench 306. In FIGS. 1 and 2, end layers 120, 124, 220, and 224 aregenerally perpendicular to a length of trenches 106 and 206,respectively. First and second layers 320 and 324 are selected so thatone of layers 320 and 324 is an n-type semiconductor and the other oflayers 320 and 324 is a p-type semiconductor. In some aspects, first endlayer 320 is an n-type semiconductor that couples to layers 310 and 314and second end layer 324 is a p-type semiconductor that couples tolayers 308, 312, and 316. In some aspects, first end layer 320 is ap-type semiconductor that couples to layers 308, 312, and 316 and secondend layer 324 is an n-type semiconductor that couples to layers 310 and314. First and second end layers 320 and 324 can be deposited usingvarious deposition techniques, including MOCVD, MBE, HVPE, evaporationdeposition, sputter deposition, LPE, and various other PVD or CVDtechniques. In step IV(c), mask 319 (and mask 318 if mask 318 was notpreviously removed) is removed.

In stage V, ohmic contacts 328 and 330 are formed. In step V(a), ohmiccontacts 328 and 330 are deposited on layers 320 and 324. Ohmic contacts328 and 330 can be formed of various metals, including Al, Ti, Ni, Au,Ta and combinations thereof. In some aspects, various surface treatmentswith acids, bases, plasmas and combinations thereof can be applied to asurface of layers 320 and 324 before the metal for the ohmic contacts328 and 330 is deposited. In some aspects, the metal(s) deposited forthe ohmic contacts 328 and 330 may be exposed to thermal anneal afterdeposition.

In exemplary embodiments, an apparatus is disclosed that may include asubstrate and a lateral superjunction device extending from thesubstrate. The lateral superjunction device may include means forproviding alternating layers n-type and p-type semiconductors. The meansfor providing alternating layers of n-type and p-type semiconductors mayinclude alternating layers of semiconductors that are stacked on top ofone another (e.g., see layers 110-114 of FIG. 1 and layers 308-316 ofFIG. 3) or alternating layers of semiconductor that are arranged next toone another (e.g., see layers 208-214 of FIG. 2). The number of layersof n-type and p-type semiconductors can vary based upon a particularapplication. The lateral superjunction device may include means forproviding electrical contacts to the alternating layers of n-type andp-type semiconductors. The means for providing electrical contacts caninclude ohmic contacts surrounding a layer of semiconductor (e.g., seelayers 120, 124 and 128, 130 of FIG. 1; see layers 220, 224 and 228, 230of FIG. 2; and see layers 320, 324 and 328, 330 of FIG. 3). In someembodiments, the electrical contacts are positioned at opposite ends ofalternating layers of semiconductor that are stacked on top of oneanother (e.g., see FIGS. 1 and 3). In some embodiments, the electricalcontacts are positioned at opposite ends of alternating layers ofsemiconductor that are arranged next to one another (e.g., see FIG. 2).

Referring now to FIG. 4, a superjunction mask 400 is illustratedaccording to aspects of the disclosure. Superjunction mask 400 includesan anode 402, a cathode 404, and a guard ring 406. A plurality ofsuperjunctions 408 connect anode 402 to cathode 404. Superjunctions 408can be implemented as superjunctions 132 or 232 discussed above.Superjunctions 132 and 232 are suited to the design of superjunctionmask 400 because superjunctions 132 and 232 include ohmic contactspositioned at their ends.

Referring now to FIG. 5, a superjunction mask 500 is illustratedaccording to aspects of the disclosure. Superjunction mask 500 includesan anode 502 and a cathode 504 that are connected via a plurality ofsuperjunctions 508. Superjunctions 508 can be implemented assuperjunction 332. Superjunction 332 is suited to the design ofsuperjunction mask 400 which includes ohmic contacts 328 and 330 thatare disposed along the sides of superjunction 332.

Referring now to FIG. 6, a graph illustrating column width versus columndoping density according to aspects of the disclosure is shown. Equation1 below describes optimum charge:

$\begin{matrix}{Q_{optimum} = {{2.7}8x10^{- 6}\frac{C}{{cm}^{2}}}} & {{Equation}\mspace{14mu} 1}\end{matrix}$

FIG. 6 illustrates that doping density can be higher for narrower columnwidths, but must be decreased as column thickness increases. As shown inFIG. 6, doping densities for the optimum charge vary from 1.00E+16 onthe low end to 1.00E+18 on the high end. This range stems from materialcharacteristics of GaN n-type and p-type semiconductors. GaN N-typesemiconductors can be manufactured with doping densities down to1.00E+16, while GaN p-type semiconductors can be manufactured withdoping densities up to 1.00E+18.

Referring now to FIG. 7, a schematic illustration of a p+ and n+ layersfor an illustrative superjunction 600 is shown. Superjunction 600includes a base layer 602, a middle layer 604, and a top layer 606. Inthe embodiment shown in FIG. 7, base layer 602 is a p-typesemiconductor, middle layer 604 is an n-type semiconductor, and toplayer 606 is a p-type semiconductor. Superjunction 600 includes endportions 608 and 610 comprised of p+-type semiconductor and n+-typesemiconductor. The designations of p+ and n+ are used to indicate higherdoping densities compared to the doping densities of layers 602-606. Insome aspects, doping densities that are ten times higher than the dopingdensities of layers 602-606 are used for end portions 608 and 610. Thehigher doping density helps facilitate conduction of electricity betweenmetallic contacts and end portions 608 and 610 to get electricity intoand out of superjunction 600, which reduces resistance and improvesperformance of superjunction 600.

In the embodiment illustrated in FIG. 7, each of layers 602-606 has athickness of around 0.5 μm and a length of around 5.0 μm. End portions608 and 610 have a height of around 1.5 μm, which corresponds to aheight of the stack of layers 602-606. In other embodiments, each oflayers 602-606 can have a thickness that ranges between 10 nanometersand 10 microns. A length each of layers 602-606 is determined based uponthe particular application. In general, dimensions of layers 602-606 andend portions 608 and 610 depends on the particular application.

As shown in FIG. 7, end portion 608 is a p-type semiconductor thatcouples to layers 602 and 606 and end portion 610 is an n-typesemiconductor that couples to layer 604. In other embodiments, baselayer 602 may be an n-type semiconductor, middle layer 604 may be ap-type semiconductor, and top layer 606 may be an n-type semiconductor.In other embodiments, end portion 608 is an n-type semiconductor thatcouples to layer 604 and end portion 610 is a p-type semiconductor thatcouples to layers 602 and 606.

Referring now to FIGS. 8-12 are graphs illustrating various performanceaspects of illustrative superjunction 600 of FIG. 7 at a doping densityof 5E+16 with layers 602-606 each having a thickness of 500 nm. FIG. 8is a graph of specific on-state resistance versus breakdown voltage forsuperjunction 600 is shown. FIG. 8 illustrates that an increase inbreakdown voltage (V) is accompanied by an increase in specificon-resistance (mΩ-cm²). Lines for Si, SiC, and GaN illustratetheoretical values based upon material properties for Si, SiC, and GaN.As illustrated in FIG. 8, superjunction 600 is able to outperform thematerial properties of GaN for breakdown voltages of betweenapproximately 400V to 1,100V.

Referring now to FIG. 9, a graph of figure of merit versus column dopingdensity is shown. Equation 2 below describes figure of merit as thesquare of breakdown voltage divided by specific on-resistance.

$\begin{matrix}{{FOM} = \frac{V_{BR}^{2}}{R_{ON}}} & {{Equation}\mspace{20mu} 2}\end{matrix}$

FIG. 9 illustrates that FOM peaks at a doping density of around 2E+16 to3E+16. In some aspects, a doping density of 3E+16 may be desirable asthe cost to manufacture a superjunction with a doping density of 3E+16instead of 2E+16 should be lower. Furthermore, FIG. 9 illustrates asmall difference between FOM values at doping densities of 3E+16 versus2E+16. Similarly, in other aspects, using doping densities of 4E+16 or5E+16 may be desirable to further lower costs while at the same timemaintaining higher FOM values versus doping densities of 6E+16 orhigher.

Referring now to FIGS. 10A and 10B, graphs of electric field versustransverse and perpendicular distances for the illustrativesuperjunction 600 of FIG. 7 are shown. FIGS. 10A and 10B were generatedusing a doping density value of 5E+16. FIG. 10A illustrates electricfield distribution along a y-axis of superjunction 600 (e.g., see lineA-A in FIG. 7). Peaks at 0.5 μm and 1 μm correspond with boundariesbetween layers 602-606. FIG. 10B illustrates electric field distributionalong an x-axis of superjunction 600 (e.g., see line B-B in FIG. 7).

Referring now to FIG. 11, a graph of current versus voltage forillustrative superjunction 600 is shown. On-state resistance ofsuperjunction 600 can be calculated by taking the slope of the curvebeyond the turn-on voltage (e.g., above around 3V). FIG. 12, is a graphof the log of the current of FIG. 11. FIG. 12 shows the magnitude ofchange in the current for the off state and the on state ofsuperjunction 600.

Referring now to FIG. 13, a graph of simulated breakdown voltage versuscharge imbalance for illustrative superjunction 600 is shown. For FIG.13, a doping density of N=5E+16 was selected and charge imbalance wasdetermined off of that value. Equation 3 below describes chargeimbalance (in percent).

$\begin{matrix}{{Imbalance} = {100\frac{N_{D} - N_{A}}{N_{D} + N_{A}}}} & {{Equation}\mspace{20mu} 3}\end{matrix}$

N_(D) represents doping density of donors in the n-type layer and NArepresents number of acceptors in the p-type layer. FIG. 13 illustratesan increase in breakdown voltage for charge imbalances greater than 0%and less than approximately 50%. Breakdown voltage is shown to peak atcharge imbalances of around 30%. Surprisingly, FIG. 13 illustrates that(and FIG. 9 confirms) greater breakdown voltages are obtainable thanbreakdown voltages of standard GaN, even at lower doping densities. Thisgreater breakdown voltage is obtainable at attainable doping levels forn-type and p-type semiconductors.

Referring now to FIG. 14, a graph comparing electric field versusdistance for the superjunction device of FIG. 13 with different chargeimbalances is shown. FIG. 14 illustrates that a charge imbalance ofaround 30% provides a much more consistent and uniform electric fieldalong a length of the superjunction compared to the 0% charge imbalancecase. This more uniform electric field is preferable as it shouldprovide longer service life for the superjunction.

Referring now to FIG. 15, a graph of doping density versus distance fordifferent graded profile values is shown. FIG. 15 illustrates the effectof diffusion of dopants between layers of n-type and p-typesemiconductors. Dopant diffusion often results as a byproduct of themanufacturing process, which subjects the superjunction to hightemperatures that provide energy for dopants to diffuse throughout thesuperjunction. In FIG. 15, G represents a Gaussian distribution ofdopant diffusion. At G=0, there is no dopant diffusion between layersand the doping density does not change between layers. At G=0.05, thereis some dopant diffusion between layers and the doping density variesthrough the superjunction. The remaining G values illustrate increaseddopant diffusion.

Referring now to FIG. 16, a graph of relative charge to baseline versusgraded profile value for superjunction of FIG. 15 is shown. FIG. 16compares relative changes to the G=0 plot of FIG. 15 to G values of0.05, 0.15, 0.25, and 0.35, where G is the standard deviation of aGaussian distribution in microns. At G=0.05, on-state resistance hasincreased significantly, which is not desirable as it lowerssuperjunction efficiency. Breakdown voltage has increased around twelvepercent, but the resulting FOM has decreased around twenty five percent.At G=0.15, on-state resistance has increased slightly, but significantlyless than at G=0.05. Breakdown voltage has increased around twelvepercent and FOM increased around twenty percent. At G=0.25, on-stateresistance actually decreases around ten percent, which is verydesirable. Breakdown voltage has increased around ten percent and FOMhas increased over twenty five percent. At G=0.35, on-state resistancehas again increased around twenty percent. Breakdown voltage increasedslightly and FOM decreased slightly. The value of G=0.25 showed thegreatest performance characteristics with decreased on-state resistance,increased breakdown voltage, and increased FOM compared to the G=0 case.

Referring now to FIG. 17, a graph of specific on-resistance versusbreakdown voltage is shown. FIG. 17 compares the data of FIG. 16 withthe data of FIG. 8 to show the impact of dopant diffusion and chargeimbalance on performance of the superjunction. The optimum charge datapoints illustrate an ideal case without dopant diffusion and chargeimbalance. The graded profile data points illustrate the performance ofthe superjunction with dopant diffusion and charge imbalance. The gradedprofile data points illustrate that performance of the superjunctionstill exceeds GaN alone. The contact resistance data point shows theeffect on superjunction performance of the losses caused by contactresistance.

Conditional language used herein, such as, among others, “can,” “might,”“may,” “e.g.,” and the like, unless specifically stated otherwise, orotherwise understood within the context as used, is generally intendedto convey that certain embodiments include, while other embodiments donot include, certain features, elements and/or states. Thus, suchconditional language is not generally intended to imply that features,elements and/or states are in any way required for one or moreembodiments or that one or more embodiments necessarily include logicfor deciding, with or without author input or prompting, whether thesefeatures, elements and/or states are included or are to be performed inany particular embodiment.

While the above detailed description has shown, described, and pointedout novel features as applied to various embodiments, it will beunderstood that various omissions, substitutions, and changes in theform and details of the devices or algorithms illustrated can be madewithout departing from the spirit of the disclosure. As will berecognized, the processes described herein can be embodied within a formthat does not provide all of the features and benefits set forth herein,as some features can be used or practiced separately from others. Thescope of protection is defined by the appended claims rather than by theforegoing description. All changes which come within the meaning andrange of equivalency of the claims are to be embraced within theirscope.

What is claimed is:
 1. A lateral superjunction comprising: a substratelayer; a nucleation layer deposited on the substrate layer; a trenchformed into the nucleation layer to expose a portion of the substratelayer; a first layer of semiconductor deposited in the trench; a secondlayer of semiconductor deposited adjacent to the first layer; and afirst end layer of semiconductor deposited adjacent to the first layerof semiconductor and a second end layer of semiconductor depositedadjacent to the second layer of semiconductor.
 2. The lateralsuperjunction of claim 1, wherein the second layer of semiconductor isstacked on top of the first layer of semiconductor.
 3. The lateralsuperjunction of claim 2, wherein the first end layer of semiconductorand the second end layer of semiconductor are positioned over thetrench.
 4. The lateral superjunction of claim 2, wherein the first endlayer of semiconductor and the second end layer of semiconductor areoriented parallel to a length of the trench.
 5. The lateralsuperjunction of claim 1, wherein the first layer of semiconductor andthe second layer of semiconductor are positioned next to one another ina side by side position.
 6. The lateral superjunction of claim 5,wherein: the first end layer of semiconductor contacts a first end ofthe first layer of semiconductor and a first end of the second layer ofsemiconductor; and the second end layer of semiconductor contacts asecond end of the first layer of semiconductor and a second end of thesecond layer of semiconductor.
 7. The lateral superjunction of claim 1,wherein the first layer of semiconductor and the first end layer ofsemiconductor comprise p-type semiconductors and the second layer ofsemiconductor and second end layer of semiconductor comprise n-typesemiconductors.
 8. The lateral superjunction of claim 1, wherein thesubstrate layer comprises at least one of silicon and sapphire.
 9. Thelateral superjunction of claim 1, wherein the nucleation layer comprisesat least one of AlN, InN, and GaN.
 10. The lateral superjunction ofclaim 1, wherein the substrate layer comprises bulk GaN.
 11. The lateralsuperjunction of claim 1, wherein the first end layer of semiconductorand the second end layer of semiconductor each comprise an ohmic contactlayer.
 12. The lateral superjunction of claim 11, wherein the ohmiccontact layers comprise at least one of Al, Ti, Ni, Au, or Ta.